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16 Input, 16 Output Analog I/O Port with Integrated Amplifiers AD5590
FEATURES
Input channels 12-bit successive approximation ADC 16 inputs with sequencer Fast throughput rate: 1 MSPS Wide input bandwidth: 70 dB SNR at fIN = 50 kHz Output channels 16 outputs with 12-bit DACs On-chip 2.5 V reference Hardware LDAC and LDAC override function CLR function to programmable code Rail-to-rail operation Operational amplifiers Offset voltage: 2.2 mV maximum Low input bias current: 1 pA maximum Single supply operation Low noise: 22 nV/Hz Unity gain stable Flexible serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible -40C to +85C operation
APPLICATIONS
Optical line cards Base stations General-purpose analog I/O Monitoring and control
FUNCTIONAL BLOCK DIAGRAM
ADCVDD DACVDD (x2) V1+ V2+ V1- V2- VREFIN1/VREFOUT1
POWER-ON RESET
LDAC INPUT REGISTER DAC REGISTER STRING DAC 0
1.25V/2.5V REF
POWER-DOWN LOGIC
BUFFER
DSCLK DSYNC1 DSYNC2 DDIN LDAC CLR DAC INTERFACE LOGIC
VOUT0
INPUT REGISTER
DAC REGISTER
STRING DAC 7
BUFFER
VOUT7
INPUT REGISTER
DAC REGISTER
STRING DAC 8
BUFFER
VOUT8
INPUT REGISTER
DAC REGISTER
STRING DAC 15
BUFFER
VOUT15
POWER-DOWN LOGIC VDRIVE 1.25V/2.5V REF SEQUENCER 12-BIT SUCCESSIVE APPROXIMATION ADC T/H INPUT MUX VREFIN2/VREFOUT2 VIN0
ASCLK ASYNC ADIN ADOUT
ADC INTERFACE LOGIC
VINI5
AD5590
IN0(-) IN0(+) OUT0 IN7(-) IN7(+) OUT7 DACGND (x2) ADCGND
VREFA
07691-001
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD5590 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 ADC Specifications ...................................................................... 4 DAC Specifications....................................................................... 6 Operational Amplifier Specifications ........................................ 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 11 Thermal Resistance .................................................................... 11 ESD Caution ................................................................................ 11 Pin Configuration and Function Descriptions ........................... 12 Typical Performance Characteristics ........................................... 14 DAC.............................................................................................. 14 ADC ............................................................................................. 18 Amplifier ..................................................................................... 19 Terminology .................................................................................... 23 Theory of Operation ...................................................................... 26 DAC Section................................................................................ 26 ADC Section ............................................................................... 27 ADC Converter Operation ....................................................... 27 Amplifier Section ....................................................................... 29 Serial Interface ................................................................................ 30 Accessing the DAC Block .......................................................... 30 Accessing the ADC Block ......................................................... 34 Outline Dimensions ....................................................................... 42 Ordering Guide .......................................................................... 42
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 44
AD5590 GENERAL DESCRIPTION
The AD5590 is a 16-channel input and 16-channel output analog I/O port with eight uncommitted amplifiers, operating from a single 4.5 V to 5.25 V supply. The AD5590 comprises 16 input channels multiplexed into a 1 MSPS, 12-bit successive approximation ADC with a sequencer to allow a preprogrammed selection of channels to be converted sequentially. The ADC contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 MHz. The conversion process and data acquisition are controlled using ASYNC and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of ASYNC and conversion is also initiated at this point. There are no pipeline delays associated with the ADC. By setting the relevant bits in the control register, the analog input range for the ADC can be selected to be a 0 V to VREFA input or a 0 V to 2 x VREFA with either straight binary or twos complement output coding. The conversion time is determined by the ASCLK frequency because it is also used as the master clock to control the conversion. The DAC section of the AD5590 comprises sixteen 12-bit DACs divided into two groups of eight. Each group has an on-chip reference. The on-board references are off at power-up, allowing the use of external references. The internal references are enabled via a software write. The AD5590 incorporates a power-on reset circuit that ensures that the DAC outputs power up to 0 V and remain powered up at this level until a valid write takes place. The DAC contains a power-down feature that reduces the current consumption of the device and provides software-selectable output loads while in power-down mode for any or all DAC channels. The outputs of all DACs can be updated simultaneously using the LDAC function, with the added functionality of user-selectable DAC channels to simultaneously update. There is also an asynchronous CLR that updates all DACs to a user-programmable code: zero scale, midscale, or full scale. The AD5590 contains eight low noise, single-supply amplifiers. These amplifiers can be used for signal conditioning for the ADCs, DACs, or other independent circuitry, if required.
Rev. 0 | Page 3 of 44
AD5590 SPECIFICATIONS
ADC SPECIFICATIONS
ADCVDD = VDRIVE = 2.7 V to 5.25 VREFA = 2.5 V, fSCLK 1 = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 3 Signal-to-Noise Ratio (SNR)3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3, 4 Second-Order Terms Third-Order Terms Aperture Delay4 Aperture Jitter4 Channel-to-Channel Isolation3, 4 Full Power Bandwidth4 DC ACCURACY3 Resolution Integral Nonlinearity Differential Nonlinearity 0 V to VREFA Input Range Offset Error Offset Error Match Gain Error Gain Error Match 0 V to 2 x VREFA Input Range Positive Gain Error Positive Gain Error Match Zero-Code Error Zero-Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Ranges Min 68.5 69 -74 -75 Typ 70 70.5 70 70.5 -82 -82 -86 -80 -85 -85 10 50 -82 8.2 1.6 12 -1 -1 -10 -2 -0.8 0.6 +1 +1.5 +10 3.5 +2 +0.8 Max Unit dB dB dB dB dB dB dB dB dB dB ns ps dB MHz MHz Bits LSB LSB LSB LSB LSB LSB -VREFA to +VREFA biased about VREFA with twos complement output coding offset -2 -0.8 -8 -1 -0.8 0 to VREFA 0 to 2 x VREFA -1 20 2.5 -1 36 +1 +1 +2 +0.8 +8 2 +1 +0.8 LSB LSB LSB LSB LSB LSB V V A pF V A k 1% specified performance fSAMPLE = 1 MSPS Range bit set to 1 Range bit set to 0, ADCVDD/VDRIVE = 4.75 V to 5.25 V for 0 V to 2 x VREFAS Test Conditions/Comments 2 fIN = 50 kHz sine wave, fSCLK = 20 MHz @5V @3V @5V @3V @5V @3V @5V @3V fa = 40.1 kHz, fb = 41.5 kHz
fIN = 400 kHz @ 3 dB @ 0.1 dB
Guaranteed no missing codes to 12 bits Straight binary output coding
0.6
DC Leakage Current Input Capacitance4 REFERENCE INPUT VREFA Input Voltage DC Leakage Current VREFA Input Impedance4
Rev. 0 | Page 4 of 44
AD5590
Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN1, 4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance4 Output Coding CONVERSION RATE 4 Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate POWER REQUIREMENTS ADCVDD VDRIVE IDRIVE IDD 5 Normal Mode, Static Normal Mode, Operational (fS = Maximum Throughput) Autostandby Mode Autoshutdown Mode Full Shutdown Mode Power Dissipation Normal Mode, Operational Autostandby Mode, Static Autoshutdown Mode, Static Full Shutdown Mode
1 2
Min 0.7 x VDRIVE -1
Typ
Max
Unit V V A pF V V A pF
Test Conditions/Comments 2
0.3 x VDRIVE +1 10
Typically 10 nA
VDRIVE - 0.2 0.4 10 10 Straight (Natural) Binary Twos Complement 800 300 300 1 2.7 2.7 5.25 5.25 0.15 750 2.5 1.55 100 960 0.02 0.5 0.5 12.5 500 2.5 2.5
ISOURCE = 200 A; VDD = 2.7 V to 5.25 V ISINK = 200 A weak/TRI bit set to 0 weak/TRI bit set to 0 coding bit set to 1 coding bit set to 0 16 ASCLK cycles, ASCLK = 20 MHz Sine wave input Full-scale step input @ 5 V (see the Serial Interface section)
ns ns ns MSPS V V A A mA mA A A A A mW W W W
Digital inputs = 0 V or VDRIVE VDD = 4.75 V to 5.25 V, ASCLK on or off VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz fSAMPLE = 500 kSPS Static fSAMPLE = 250 kSPS Static ASCLK on or off ADCVDD = 5 V, fSCLK = 20 MHz ADCVDD = 5 V ADCVDD = 5 V ADCVDD = 5 V
Specifications apply for fSCLK up to 20 MHz. For serial interfacing requirements, see the Timing Specifications section. Temperature range: -40C to +85C. 3 See the Terminology section. 4 Guaranteed by design and characterization. Not production tested. 5 See the ADC Power vs. Throughput Rate section.
Rev. 0 | Page 5 of 44
AD5590
DAC SPECIFICATIONS
DACVDD = 4.5 V to 5.25 V, RL = 2 k to DACGND, CL = 200 pF to DACGND, VREFIN1 = VREFIN1 = DACVDD. All specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter STATIC PERFORMANCE 2 Resolution Integrated Nonlinearity (INL) Differential Nonlinearity (DNL) Zero-Code Error Zero-Code Error Drift3 Full-Scale Error Gain Error Gain Temperature Coefficient3 Offset Error DC Power Supply Rejection Ratio3 DC Crosstalk 3 External Reference Min 12 -3 -0.25 Typ Max Unit Bits LSB LSB mV V/C % FSR % FSR ppm mV dB V V/mA V V V/mA DACVDD 2 10 0.5 30 4 40 0 14.6 2.495 10 7.5 -3 2 5 +3 0.8 2.505 50 DACVDD V nF nF mA s A V k V ppm/C k A V V pF Conditions/Comments 1
0.5 1 2 -0.2 2.5 5 -80 10 5 10 25 10
+3 +0.25 12
See Figure 6 Guaranteed monotonic by design; see Figure 7 All 0s loaded to DAC register; see Figure 11 All 1s loaded to DAC register Of FSR/C DACVDD 10% Due to full-scale output change, RL = 2 k to DACGND or DACVDD Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 k to DACGND or DACVDD Due to load current change
-1 -1 -11
+1 +11
Internal Reference
OUTPUT CHARACTERISTICS3 Output Voltage Range Capacitive Load Stability DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance3 REFERENCE OUTPUT Output Voltage Reference Temperature Coefficient3 Reference Output Impedance3 LOGIC INPUTS Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance3
0
RL = RL = 2 k DACVDD = 5 V Coming out of power-down mode, DACVDD = 5 V VREFINx = DACVDD = 5.5 V (per DAC channel)
At ambient
All digital inputs DACVDD = 5 V DACVDD = 5 V
Rev. 0 | Page 6 of 44
AD5590
Parameter POWER REQUIREMENTS DACVDD IDD (Normal Mode) 4 2.6 4 DACIDD (All Power-Down Modes) 5 DACVDD
1 2
Min 4.5
Typ
Max 5.5
Unit V
Conditions/Comments 1 All digital inputs at 0 or DACVDD, DAC active, excludes load current VIH = DACVDD = 4.5 V to 5.5 V, VIL = DACGND Internal reference off Internal reference on VIH = DACVDD = 4.5 V to 5.5 V, VIL = DACGND
3.2 5 2
mA mA A
0.8
Temperature range is -40C to +85C, typical at 25C. Linearity calculated using a reduced code range of Code 32 to Code 4064. Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All sixteen DACs powered down.
DAC AC Characteristics
DACVDD = 4.5 V to 5.25 V, RL = 2 k to DACGND, CL = 200 pF to DACGND, VREFIN1 = VREFIN1 = DACVDD. All specifications TMIN to TMAX, unless otherwise noted. Table 3.
Parameter 1, 2 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Reference Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise
1 2
Min
Typ 6 1.5 4 0.1 -90 0.5 2.5 3 340 -80 120 100 15
Max 10
Unit s V/s nV-sec nV-sec dB nV-sec nV-sec nV-sec kHz dB nV/Hz nV/Hz V p-p
Conditions/Comments 3 1/4 to 3/4 scale settling to 2 LSB 1 LSB change around major carry (see Figure 17) VREFIN1 = VREFIN2 = 2 V 0.1 V p-p, frequency = 10 Hz to 20 MHz
VREFIN1 = VREFIN2 = 2 V 0.2 V p-p VREFIN1 = VREFIN2 = 2 V 0.1 V p-p, frequency = 10 kHz DAC Code = 0x8400, 1 kHz DAC Code = 0x8400, 10 kHz 0.1 Hz to 10 Hz
Guaranteed by design and characterization; not production tested. See the Terminology section. 3 Temperature range is -40C to +85C, typical at 25C.
Rev. 0 | Page 7 of 44
AD5590
OPERATIONAL AMPLIFIER SPECIFICATIONS
Electrical characteristics @ VSY = 5 V, VCM = VSY/2, TA = 25C, unless otherwise noted. Table 4.
Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift 1 Input Bias Current1 Input Offset Current1 Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance1 OUTPUT CHARACTERISTICS Output Voltage High Symbol VOS VOS/T IB IOS CMRR AVO CDIFF CCM VOH 68 235 Min Typ 0.4 1 0.2 0.1 95 400 2 7 4.98 4.7 4.50 Output Voltage Low VOL 20 190 Short-Circuit Current1 Closed-Loop Output Impedance1 POWER SUPPLY Power Supply Span (V+ to V-) Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE1 Slew Rate Settling Time 0.1% Gain Bandwidth Product Phase Margin NOISE PERFORMANCE1 Peak-to-Peak Noise Voltage Noise Density Current Noise Density
1
Max 2.2 2.2 4.5 1 110 0.5 50
Unit mV mV V/C pA pA pA pA dB dB V/mV pF pF V V V V mV mV mV mV mA V dB dB A A V/s s kHz kHz Degrees
Conditions -0.3 V < VCM < +5.3 V -40C < TA < +85C, -0.3 V < VCM < +5.2 V -40C < TA < +85C -40C < TA < +85C -40C < TA < +85C 0 V < VCM < 5 V -40C < TA < +85C RL = 10 k, 0.5 V < VOUT < 4.5 V
4.95 4.9
30 50 275 335
IL = 1 mA -40C to +85C IL = 10 mA -40C to +85C IL = 1 mA -40C to +85C IL = 10 mA -40C to +85C f = 10 kHz, AV = 1
ISC ZOUT
80 15 5 94 38 50 0.1 23 400 350 70 2.3 25 22 0.05 3.5
PSRR ISY
67 64
60
1.8 V < VSY < 5 V -40C < TA < +85C VOUT = VSY/2 -40C SR tS GBP OO
en in
V nV/Hz nV/Hz pA/Hz
f = 1 kHz f = 10 kHz f = 1 kHz
Guaranteed by design and characterization. Not production tested.
Rev. 0 | Page 8 of 44
AD5590
TIMING SPECIFICATIONS
ADC Timing Characteristics
ADCVDD = 2.7 V to 5.25 V, VDRIVE ADCVDD, VREFA = 2.5 V; All specifications TMIN to TMAX, unless otherwise noted. Table 5.
Parameter 1 fSCLK 2 tCONVERT tQUIET t2 t3 3 t3b 4 t43 t5 t6 t7 t8 5 t9 t10 t11 t12
1
Limit at TMIN, TMAX; ADCVDD = 5 V 10 20 16 x tASCLK 50 10 14 20 40 0.4 x tASCLK 0.4 x tASCLK 15 15/50 20 5 20 1
Unit kHz min MHz min MHz max ns min ns min ns max ns min ns max ns min ns min ns min ns min/max ns min ns min ns min s max
Conditions/Comments
ASYNC to ASCLK setup time Delay from ASYNC until ADOUT three-state disabled Data hold time Data access time after ASCLK falling edge ASCLK low pulse width ASCLK high pulse width ASCLK to ADOUT valid hold time ASCLK falling edge to ADOUT high impedance ADIN setup time prior to ASCLK falling edge ADIN Hold time prior to ASCLK falling edge 16th ASCLK falling edge to ASYNC high Power-up time from full power-down/autoshutdown/ autostandby modes
Guaranteed by design and characterization. Not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of ADCVDD) and timed from a voltage level of 1.6 V. 2 Maximum ASCLK frequency is 50 MHz at ADCVDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. 3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 x VDRIVE. 4 t3b represents a worst-case figure for having ADD3 available on the ADOUT line, that is, if the ADC goes back into three-state at the end of a conversion and some other device takes control of the bus between conversions, the user needs to wait a maximum time of t3b before having ADD3 valid on the ADOUT line. If the ADOUT line is weakly driven to ADD3 between conversions, then the user typically needs to wait 17 ns at 3 V and 12 ns at 5 V after the ASYNC falling edge before seeing ADD3 valid on ADOUT. 5 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of bus loading.
ASYNC
t2
ASCLK 1 2 3 4
t6 t3b
ADD2 ADD1
tCONVERT
5 6 13
B
14
15
16
t3
ADOUT THREESTATE ADD3 WRITE
t4
ADD0 DB11
t7
DB10 DB2
t5
DB1
t11
DB0
tQUIET
07691-002
t9
SEQ
FOUR IDENTIFICATION BITS ADD3 ADD2
t10
ADD1 ADD0 DONTC DONTC
t8
DONTC
THREESTATE
ADIN
Figure 2. ADC Timing Characteristics
200A
IOL
TO OUTPUT PIN
1.6V CL 25pF 200A IOH
07691-003
Figure 3. Load Circuit for ADC Digital Output Timing Specifications
Rev. 0 | Page 9 of 44
AD5590
DAC Timing Characteristics
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4. DACVDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 6.
Parameter 1 t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15
1 2
Limit at TMIN, TMAX; DACVDD = 2.7 V to 5.5 V 20 8 8 13 4 4 0 15 13 0 10 15 5 0 300
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns typ
Conditions/Comments DSCLK cycle time DSCLK high time DSCLK low time DSYNC to DSCLK falling edge setup time Data setup time Data hold time DSCLK falling edge to DSYNC rising edge Minimum DSYNC high time DSYNC rising edge to DSCLK fall ignore DSCLK falling edge to DSYNC fall ignore LDAC pulse width low DSCLK falling edge to LDAC rising edge CLR pulse width low DSCLK falling edge to LDAC falling edge CLR pulse activation time
Sample tested at 25C to ensure compliance. Maximum DSCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
t10
DSCLK
t1
t9
t8
DSYNCx
t4
t3
t2
t7
t5
DDIN DB31
t6
DB0
t14
LDAC1
t11
t12
LDAC2 CLR
t13 t15
VOUTx
1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE.
Figure 4. DAC Timing Characteristics
Rev. 0 | Page 10 of 44
07691-004
AD5590 ABSOLUTE MAXIMUM RATINGS
TA = 25C unless otherwise noted. VDD refers to DACVDD or ADCVDD. GND refers to DACGND or ADCGND. Table 7.
Parameter VDD to GND VDRIVE to GND Op Amp Supply Voltage Op Amp Input Voltage Op Amp Differential Input Voltage Op Amp Output Short-Circuit Duration to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND VREFA to GND VREFIN/VREFOUT to GND Input Current to Any ADC Pin Except Supplies Operating Temperature Range Storage Temperature Range Junction Temperature (TJ max) Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V 6V (V1- or V2-) - 0.3 V to (V1+ or V2+) + 0.3 V 6 V Indefinite -0.3 V to VDD + 0.3 V -0.3 V to +7 V -0.3 V to VDD +0.3 V -0.3 V to VDD +0.3 V -0.3 V to VDD +0.3 V 10 mA -40C to +85C -65C to +150C 150C
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a 4-layer JEDEC thermal test board for surfacemount packages. Table 8. Thermal Resistance
Package Type 80-Ball CSP_BGA JA 40 Unit C/W
Table 9. Junction Temperature
Parameter Junction Temperature1, 2
1 2
Max 130
Unit C
Comments TJ = TA + PTOTAL x JA
PTOTAL is the sum of ADC, DAC, and operational amplifier supply currents. JA is the package thermal resistance.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 11 of 44
AD5590 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12 11 10 9 8 7 6 5 4 3 2 1 VOUT14 VOUT10 VOUT8 DACGND LDAC DDIN DSCLK DSYNC1 DACV DD VOUT5 VOUT7 VOUT0 A
VIN12
VIN10
VOUT12
VOUT1
DACV DD DSYNC2
CLR
DACGND VOUT3
VIN9
VIN8
OUT2
B
OUT7
VOUT9
VOUT2
IN2(+)
C
IN7(-)
VOUT11
VOUT4
IN2(-)
D
IN7(+)
VOUT13
VOUT6
IN3(+)
E
IN6(+)
VOUT15
VREFIN1 / VREFOUT1
IN3(-)
F
IN6(-)
VREFIN2 / VREFOUT2
VIN5
OUT3
G
V2-
VIN15
V1-
OUT1
H
OUT6
VREFA
VIN7
IN1(-)
J
OUT5
VIN14
VIN6
IN1(+)
K
IN5(-)
VIN11
VIN13
V2+
ADIN
ASCLK
VDRIVE
VIN1
VIN3
VIN2
VIN4
OUT0
L
IN5(+)
IN4(+)
IN4(-)
OUT4
ADCV DD ASYNC
ADOUT ADCGND
VIN0
V1+
IN0(+)
IN0(-)
M
Figure 5. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. M7 J11 M8 M5 M4, L5, L3, L4, L2, G2, K2, J2, B2, B3, B11, L11, B12, L10, K11, H11 Mnemonic ASYNC VREFA ADCVDD ADCGND VIN0 to VIN15 Description Frame Synchronization Signal. Active low logic input. This input provides the dual function of initiating ADC conversions and also frames the serial data transfer. Reference Input for the ADC Block. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V 1% for specified performance. Power Supply Input for the ADC Block. The ADC can operate from 4.5 V to 5.25 V, and the supply should be decoupled with a 10 F in parallel with a 0.1 F capacitor to ADCGND. Ground Reference Point for the ADC Block. All ADC analog/digital input/output signals and any external reference signal should be referred to this ADCGND voltage. Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are multiplexed into the on-chip track and hold. The analog input channel to be converted is selected by using the ADD3 through ADD0 address bits of the control register. The address bits in conjunction with the SEQ and shadow bits allow the sequence register to be programmed. The input range for all input channels can extend from 0 V to VREFA or 0 V to 2 x VREFA, as selected via the range bit in the control register. Any unused input channels should be connected to GND to avoid noise pickup. ADC Data In. Logic input. Data to be written to the control register of the ADC is provided on this input and is clocked into the register on the falling edge of ASCLK (see the Accessing the ADC Block section). Data Out. Logic output. The conversion result from the ADC block is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the ASCLK input. The data stream consists of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, which is provided MSB first. The output coding can be selected as straight binary or twos complement via the coding bit in the control register.
Rev. 0 | Page 12 of 44
L8 M6
ADIN ADOUT
07691-005
AD5590
Pin No. L7 L6 A4, B8 Mnemonic ASCLK VDRIVE DACVDD Description Serial Clock. Logic input. ASCLK provides the serial clock for accessing data from the ADC block. This clock input is also used as the clock source for the conversion process of the ADC. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the ADC block operates. Power Supply Input for the DAC Block. The DAC can operate from 4.5 V to 5.25 V, and the supply should be decoupled with a 10 F in parallel with a 0.1 F capacitor to DACGND. The two DACVDD pins must be connected together. Ground Reference Point for the DAC Block. All DAC analog/digital input/output signals and any external reference signal should be referred to this DACGND voltage. The two DACGND pins should be connected together. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. Active Low Control Input. This is the frame synchronization signal for the input data of DAC channels VOUT0 to VOUT7. When DSYNC1 goes low, it powers on the DSCLK and DDIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 32 clocks. If DSYNC1 is taken high before the 32nd falling edge, the rising edge of DSYNC1 acts as an interrupt and the write sequence is ignored by the device. Active Low Control Input. This is the frame synchronization signal for the input data of DAC channels VOUT8 to VOUT15. When DSYNC2 goes low, it powers on the DSCLK and DDIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 32 clocks. If DSYNC2 is taken high before the 32nd falling edge, the rising edge of DSYNC2 acts as an interrupt and the write sequence is ignored by the device. Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register--zero scale, midscale, or full scale. Default setting clears the output to 0 V. DAC Data Input. This DAC has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. DAC Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Analog Output Voltage from DAC0 to DAC7. DSYNC1 is the frame synchronization signal for writing data to these DACs. The DAC is updated automatically if LDAC is low, or on the falling edge of LDAC if it is high. The output amplifiers have rail-to-rail operation. Analog Output Voltage from DAC8 to DAC15. DSYNC2 is the frame synchronization signal for writing data to these DACs. The DAC is updated automatically if LDAC is low, or on the falling edge of LDAC if it is high. The output amplifiers have rail to rail operation. Reference Input/Output Pin for DAC0 to DAC7. The DACs have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. Reference Input/Output Pin for DAC8 to DAC15. The DACs have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. Positive Supply Input for the amplifier 0 to amplifier 3. The supply for these amplifiers is independent of other supplies and can be operated with a different supply if required. The pin should be decoupled to V1- with a 10 F in parallel with a 0.1 F capacitor. Negative Supply Input for Amplifier 0 to Amplifier 3. Positive Supply Input for Amplifier 4 to Amplifier 7. The supply for these amplifiers is independent of other supplies and can be operated with a different supply if required. The pin should be decoupled to V2- with a 10 F in parallel with a 0.1 F capacitor. Negative Supply Input for Amplifier 4 to Amplifier 7. Inverting Input Terminals for Operational Amplifier 0 to Amplifier 7. Noninverting Input Terminals for Operational Amplifier 0 to Amplifier 7. Output Terminals for Operational Amplifier 0 to Amplifier 7.
A9, B5
DACGND
A8
LDAC
A5
DSYNC1
B7
DSYNC2
B6
CLR
A7 A6 A1, B9, C2, B4, D2, A3, E2, A2 A10, C11, B11, D11, B10, E11, A12, F11 F2
DDIN DSCLK VOUT0 to VOUT7 VOUT8 to VOUT15 VREFIN1/ VREFOUT1 VREFIN2/ VREFOUT2 V1+
G11
M3
H2 L9
V1- V2+
H12 M1, J1, D1, F1, M10, L12, G12, D12 M2, K1, C1, E1, M11, M12, F12, E12 L1, H1, B1, G1, M9, K12, J12, C12
V2- IN0(-) to IN7(-) IN0(+) to IN7(+) OUT0 to OUT7
Rev. 0 | Page 13 of 44
AD5590 TYPICAL PERFORMANCE CHARACTERISTICS
DAC
DACVDD and ADCVDD = 5 V, VSY = 5 V, unless otherwise noted.
1.0 DACV DD = VREF = 5V 0.8 TA = 25C 0.6
DNL ERROR (LSB)
0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15
07691-006
07691-009
DACVDD = 5V VREFOUT = 2.5V TA = 25C
0.4
INL ERROR (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
-0.20
0
500
1000
1500
2000 2500 CODE
3000
3500
4000
Figure 6. DAC INL, External Reference
Figure 9. DAC DNL, Internal Reference
0.20 0.15 0.10
DNL ERROR (LSB)
DACV DD = VREF = 5V TA = 25C
0 -0.02 -0.04 -0.06 DACV DD = 5V
GAIN ERROR
0.05 0 -0.05 -0.10 -0.15
07691-007
ERROR (% FSR)
-0.08 -0.10 -0.12 -0.14 -0.16 -0.18 FULL-SCALE ERROR
0
500
1000
1500
2000 2500 CODE
3000
3500
4000
-20
0
20 40 60 TEMPERATURE (C)
80
100
Figure 7. DAC DNL, External Reference
Figure 10. DAC Gain Error and Full-Scale Error vs. Temperature
1.0 0.8 0.6
INL ERROR (LSB)
1.5 DACVDD = 5V VREFOUT = 2.5V TA = 25C 1.0 0.5 ZERO-SCALE ERROR
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
07691-008
ERROR (mV)
0 -0.5 -1.0 -1.5 OFFSET ERROR -2.0
07691-011
-1.0
0
500
1000
1500
2000 2500 CODE
3000
3500
4000
-2.5 -40
-20
0
20 40 60 TEMPERATURE (C)
80
100
Figure 8. DAC INL, Internal Reference
Figure 11. DAC Zero-Scale Error and Offset Error vs. Temperature
Rev. 0 | Page 14 of 44
07691-010
-0.20
-0.20 -40
AD5590
0.50 0.40 0.30 DAC LOADED WITH FULL-SCALE SOURCING CURRENT DAC LOADED WITH ZERO-SCALE SINKING CURRENT
DACV DD = VREFA = 5V TA = 25C
ERROR VOLTAGE (V)
0.20 0.10 0 -0.10 -0.20 -0.30 -0.40
07691-012
DACV DD 1
DACV DD = 5V VREFOUT = 2.5V
MAX(C2)* 420.0mV 2 VOUT
07691-015
07691-016
-0.50 -10
-8
-6
-4
-2 0 2 CURRENT (mA)
4
6
8
10
CH1 2.0V
CH2 500mV
M100s 125MS/s A CH1 1.28V
8.0ns/pt
Figure 12. DAC Headroom at Rails vs. Source and Sink
Figure 15. DAC Power-On Reset to 0 V
6 5 4 3 2 1/4 SCALE 1 0 -1 -30 2 DACV DD = 5V VREFOUT = 2.5V TA = 25C FULL SCALE 1 3/4 SCALE 3
DSYNC
DSCLK
VOUT (V)
MIDSCALE
VOUT ZERO SCALE
07691-013
DACV DD = 5V -20 -10 0 10 CURRENT (mA) 20 30 CH1 5.0V CH3 5.0V CH2 500mV M400ns A CH1 1.4V
Figure 13. DAC Sink and Source Capability
Figure 16. DAC Exiting Power-Down to Midscale
VOUT = 909mV/DIV 1
07691-014
VOUT (V)
DACV DD = VREFA = 5V TA = 25C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2k AND 200pF TO GND
TIME BASE = 4s/DIV
0
64
128
192
256 320 SAMPLE
384
448
512
Figure 14. DAC Full-Scale Settling Time
Figure 17. DAC Digital-to-Analog Glitch Impulse (Negative)
Rev. 0 | Page 15 of 44
07691-017
2.505 2.504 2.503 2.502 2.501 2.500 2.499 2.498 2.497 2.496 2.495 2.494 2.493 2.492 2.491 2.490 2.489 2.488 2.487 2.486 2.485
DACV DD = 5V VREFOUT = 2.5V TA = 25C 4ns/SAMPLE NUMBER GLITCH IMPULSE = 3.55nV-sec 1 LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF)
AD5590
2.5000 2.4995 2.4990 2.4985 DACV DD = 5V VREFOUT = 2.5V TA = 25C DAC LOADED WITH MIDSCALE
VOUT (V)
10V/DIV
DACV DD = 5V VREFOUT = 2.5V TA = 25C 4ns/SAMPLE NUMBER
07691-018
2.4980 2.4975 2.4970 2.4965 2.4960 2.4955 2.4950 0 64 128 192
1
256 320 SAMPLE
384
448
512
5s/DIV
Figure 18. DAC Analog Crosstalk
Figure 20. 0.1 Hz to 10 Hz DAC Output Noise Plot, Internal Reference
2.4900 2.4895
800 700
TA = 25C MIDSCALE LOADED
2.4885
OUTPUT NOISE (nV/Hz)
2.4890
600 500 400 300 200 100
07691-021
VOUT (V)
2.4880 2.4875 2.4870 2.4865 2.4860 2.4855 DACV DD = 5V VREFOUT = 2.5V TA = 25C 4ns/SAMPLE NUMBER
07691-019
DACV DD = 5V VREFOUT = 2.5V
0
64
128
192
256 320 SAMPLE
384
448
512
0 100
1000
10000 FREQUENCY (Hz)
100000
1000000
Figure 19. DAC-to-DAC Crosstalk
Figure 21. DAC Noise Spectral Density, Internal Reference
Rev. 0 | Page 16 of 44
07691-020
AD5590
-20 -30 -40 -50 DACV DD = 5V TA = 25C DAC LOADED WITH FULL SCALE VREF = 2V 0.3V p-p 5 0 -5 -10 -15 -20 -25 -30 -35
07691-022 07691-024
DACV DD = 5V TA = 25C
(dB)
-60 -70 -80 -90 -100
(dB)
2k
4k 6k FREQUENCY (Hz)
8k
10k
-40 10k
100k 1M FREQUENCY (Hz)
10M
Figure 22. DAC Total Harmonic Distortion
Figure 24. DAC Multiplying Bandwidth
16
VREFIN = DACVDD TA = 25C
14
12
TIME (s)
10
8
DACV DD = 5V
6
0
1
2
3
4 5 6 7 CAPACITANCE (nF)
8
9
10
Figure 23. DAC Settling Time vs. Capacitive Load
07691-023
4
Rev. 0 | Page 17 of 44
AD5590
ADC
DACVDD and ADCVDD = 5 V, VSY = 5 V, unless otherwise noted.
5 8192 POINT FFT fSAMPLE = 1MSPS fIN = 50kHZ SINAD = 70.697dB THD = -79.171dB SFDR = -79.93dB -50 TA = 25C -55 ADCV DD = 5.25V RANGE = 0V TO REFIN -60 -65
fS = 1MSPS
-15
RIN = 1000
-35
(dB)
-55
(dB)
-70 RIN = 100 -75 RIN = 5 -80 RIN = 10 -85 10
-75
-95
07691-025
0
50
100
150
200
250
300
350
400
450
500
100 INPUT FREQUENCY (Hz)
1000
FREQUENCY (kHz)
Figure 25. ADC Dynamic Performance at 1 MSPS
Figure 28. ADC THD vs. Input Frequency for Various Analog Source Impedances
1.0 ADCV DD = VDRIVE = 5V 0.8 TEMPERATURE = 25C
75
ADCV DD = VDRIVE = 5.25V 70 ADCV DD = VDRIVE = 4.75V
(dB) INL ERROR (LSB)
0.6 0.4 0.2 0 -0.2 -0.4 -0.6
65
60
fS = MAX THROUGHPUT
55 10 TA = 25C RANGE = 0V TO VREFA
-0.8
07691-026
100 INPUT FREQUENCY (kHz)
1000
0
512
1024
1536
2048 CODE
2560
3072
3584
4096
Figure 26. ADC SINAD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS
-50 -55 -60
Figure 29. ADC Typical INL
fS = MAX THROUGHPUT
TA = 25C RANGE = 0V TO REFIN
1.0 ADCV DD = VDRIVE = 5V 0.8 TEMPERATURE = 25C 0.6 0.4
DNL ERROR (LSB)
-65
0.2 0 -0.2 -0.4 -0.6 -0.8
(dB)
-70 -75 -80 -85 -90 10
ADCV DD = VDRIVE = 4.75V ADCV DD = VDRIVE = 5.25V
07691-027
100 INPUT FREQUENCY (kHz)
1000
0
512
1024
1536
2048 CODE
2560
3072
3584
4096
Figure 27. THD vs. Analog Input Frequency for Various Supplies at 1 MSPS
Figure 30. ADC Typical DNL
Rev. 0 | Page 18 of 44
07691-030
-1.0
07691-029
-1.0
07691-028
AD5590
AMPLIFIER
DACVDD and ADCVDD = 5 V, VSY = 5 V, unless otherwise noted.
1800 VSY = 5.5V -0.5V < V < +5.5V 1600 T = 25CCM A 400 VSY = 5V 350
1200 1000 800 600 400 200 0
INPUT BIAS CURRENT (pA)
NUMBER OF AMPLIFIERS
1400
300 250 200 150 100 50 0 25
-1100
100
400
-800
-500
-200
700
1000
1300
1600
-2000
-1700
-1400
1900
50
75
100
125
150
07691-031
TEMPERATURE (C)
INPUT OFFSET VOLTAGE (V)
Figure 31. Amplifier Input Offset Voltage Distribution
Figure 34. Amplifier Input Bias Current vs. Temperature
40 35
-40C < TA < +125C VCM = 2.5V
50
VSY = 2.5V
AMPLIFIER SUPPLY CURRENT (A)
40
NUMBER OF AMPLIFIERS
30 25 20 15 10 5 0
30
20
10
07691-032
0
1
2
3
4
5
6
7
8
9
10
-10
20
50
80
110
TCVOS (V/C)
TEMPERATURE (C)
Figure 32. Amplifier Input Offset Voltage Drift Distribution
Figure 35. Amplifier Supply Current vs. Temperature
2000 1500
VSY = 5V TA = 25C
1k
VSY = 5V TA = 25C VSY - VOH SOURCE
OUTPUT SATURATION VOLTAGE (mV)
INPUT OFFSET VOLTAGE (V)
100
1000 500 0 -500
10
1 SINK 0.1 VOL
-1000 -1500 -2000 -0.5
07691-033
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.01
0.1 LOAD CURRENT (mA)
1
10
INPUT COMMON-MODE VOLTAGE (V)
Figure 33. Amplifier Input Offset Voltage vs. Input Common-Mode Voltage
Figure 36. Amplifier Output Saturation Voltage vs. Load Current
Rev. 0 | Page 19 of 44
07691-036
0.01 0.001
07691-035
0 -40
07691-034
AD5590
40 VSY = 5V
120
VSY = 5V TA = 25C
OUTPUT SATURATION VOLTAGE (mV)
100
30 VSY - VOH @ 1mA
80 CMRR (dB)
20 VOL @ 1mA 10
60
40
20
-25
-10
5
20
35
50
65
80
95
110
125
1k
10k FREQUENCY (Hz)
100k
1M
TEMPERATURE (C)
Figure 37. Amplifier Output Saturation Voltage vs. Temperature (IL = 1 mA)
Figure 40. Amplifier CMRR vs. Frequency
350
VSY = 5V
120
OUTPUT SATURATION VOLTAGE (mV)
300 VDD - VOH @ 10mA 250
VSY = 2.5V TA = 25C
100
80
200 150 100 50 0 -40 VOL @ 10mA
PSRR (dB)
60
40
20
-25
-10
5
20
35
50
65
80
95
110
125
1k
10k FREQUENCY (Hz)
100k
1M
TEMPERATURE (C)
Figure 38. Amplifier Output Saturation Voltage vs. Temperature (IL = 10 mA)
Figure 41. Amplifier PSRR vs. Frequency
60 50 40 30 20 10 0 -10 -20 1k VSY = 2.5V RL = 100k CL = 20pF 10k 100k
135
1k AV = 100 OUTPUT IMPEDANCE () 100 AV = 10 10 AV = 1
OPEN-LOOP GAIN (dB)
90
M
45
0
OPEN-LOOP PHASE SHIFT (Degrees)
1
07691-039
1k
10k FREQUENCY (Hz)
100k
1M
FREQUENCY (Hz)
Figure 39. Amplifier Open-Loop Gain and Phase vs. Frequency
Figure 42. Amplifier Closed-Loop Output Impedance vs. Frequency
Rev. 0 | Page 20 of 44
07691-042
-45 1M
0 100
VSY = 5V
07691-041
07691-038
0 100
07691-040
07691-037
0 -40
0 100
AD5590
50 VSY = 5V 45 TA = 25C 0
SMALL SIGNAL OVERSHOOT (%)
40 35 30 25 20 15 10 5 100 LOAD CAPACITANCE (pF) 1000
07691-043
VOUT (V)
VSY = 2.5V AV = -50
-2.5 -OS 100
+OS
VIN (mV)
0
07691-046
0 10
TIME (20s/DIV)
Figure 43. Small Signal Overshoot vs. Load Capacitance
Figure 46. Amplifier Positive Overload Recovery
VOLTAGE (50mV/DIV)
VOUT (V)
VSY = 5V AV = 1 RL = 10k CL = 200pF
2.5
VSY = 2.5V AV = -50
0
0
07691-044
VIN (mV)
-100
07691-047 07691-048
TIME (4s/DIV)
TIME (20s/DIV)
Figure 44. Amplifier Small Signal Transient Response
Figure 47. Amplifier Negative Overload Recovery
VSY = 5V AV = 1 RL = 10k CL = 200pF
VIN
VOUT
VOLTAGE (1V/DIV)
VOLTAGE (1V/DIV)
TIME (20s/DIV)
07691-045
VSY = 2.5V AV = 1 RL = 10k VIN = 6V p-p TIME (20s/DIV)
Figure 45. Amplifier Large Signal Transient Response
Figure 48. Amplifier, No Phase Reversal
Rev. 0 | Page 21 of 44
AD5590
VSY = 5V 140 VSY = 5V 120 CHANNEL SEPARATION (dB)
07691-049
VOLTAGE NOISE (1V/DIV)
100 80 60 40 20 0 100
1k
10k FREQUENCY (Hz)
100k
1M
Figure 49. Amplifier 0.1 Hz to 10 Hz Input Voltage Noise
Figure 51. Amplifier Channel Separation
1000
VSY = 5V TA = 25C
INPUT VOLTAGE NOISE (nV/Hz)
100
10
1/F CORNER @ 100Hz
1
10
100 FREQUENCY (Hz)
1000
10000
Figure 50. Amplifier Voltage Noise Density
Rev. 0 | Page 22 of 44
07691-050
1
07691-051
TIME (1s/DIV)
AD5590 TERMINOLOGY
DAC Integrated Nonlinearity For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. DAC Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. The DAC is guaranteed monotonic by design. DAC Offset Error Offset error is a measure of the difference between the actual VOUT and the ideal VOUT, expressed in millivolts in the linear region of the transfer function. It can be negative or positive and is expressed in millivolts. DAC Zero-Code Error Zero-code error is a measure of the output error when zero code (0x0000) is loaded into the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in millivolts. DAC Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. DAC Zero-Code Error Drift Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in microvolts per degree Celsius. DAC Gain Error Drift Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in ppm of full-scale range per degree Celsius. DAC Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed as a percentage of the full-scale range. Figure 10 shows a plot of typical full-scale error vs. temperature. DAC Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). DAC DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in DACVDD for full-scale output of the DAC. It is measured in decibels. VREFIN is held at 2 V, and DACVDD is varied 10%. DAC DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in microvolts. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in microvolts per milliamp. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (that is, LDAC is high). It is expressed in decibels. DAC Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device, but is measured when the DAC is not being written to (SYNC held high). It is specified in nV-sec and measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa. DAC Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-sec. DAC Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping LDAC high, and then pulsing LDAC low and monitoring the output of the DAC whose digital code has not changed. The area of the glitch is expressed in nV-sec. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec.
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AD5590
Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. DAC Total Harmonic Distortion (THD) Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels. ADC Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. ADC Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. ADC Offset Error This is the deviation of the first code transition (00...000 to 00...001) from the ideal, that is, ADCGND + 1 LSB. ADC Offset Error Match This is the difference in offset error between any two channels. ADC Gain Error This is the deviation of the last code transition (111...110 to 111...111) from the ideal (that is, VREFA - 1 LSB) after the offset error has been adjusted out. ADC Gain Error Match This is the difference in gain error between any two channels. ADC Zero-Code Error This applies when using the twos complement output coding option, in particular to the 2 x VREFA input range with-VREFA to +VREFA biased about the VREFA point. It is the deviation of the midscale transition (all 0s to all 1s) from the ideal VIN voltage, that is, VREFA - 1 LSB. ADC Zero-Code Error Match This is the difference in ADC zero-code error between any two channels. ADC Positive Gain Error This applies when using the twos complement output coding option, in particular to the 2 x VREFA input range with -VREFA to +VREFA biased about the VREFA point. It is the deviation of the last code transition (011...110 to 011...111) from the ideal (that is, +VREFA - 1 LSB) after the zero-code error has been adjusted out. ADC Positive Gain Error Match This is the difference in ADC positive gain error between any two channels. ADC Negative Gain Error This applies when using the twos complement output coding option, in particular to the 2 x VREFA input range with -VREFA to +VREFA biased about the VREFA point. It is the deviation of the first code transition (100...000 to 100...001) from the ideal (that is, -VREFA + 1 LSB) after the ADC zero-code error has been adjusted out. ADC Negative Gain Error Match This is the difference in negative gain error between any two channels. ADC Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 400 kHz sine wave signal to all 15 nonselected input channels and determining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure is given worst case across all 16 channels for the ADC. ADC PSR (Power Supply Rejection) Variations in power supply affect the full scale transition, but not the linearity of the converter. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value (see the Typical Performance Characteristics section). ADC Track-and-Hold Acquisition Time The track-and-hold amplifier returns into track on the 14th ASCLK falling edge. Track-and-hold acquisition time is the minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within 1 LSB of the applied input signal, given a step change to the input signal. ADC Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the analog-to-digital converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by
Signal - to - (Noise + Distortion) = 6.02 N + 1.76 [dB] Thus, for a 12-bit converter, this is 74 dB.
ADC Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the ADC, it is defined as
THD [dB] = 20 x log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics.
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AD5590
ADC Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. ADC Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa - fb), while the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). The ADC is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves whereas the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels.
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AD5590 THEORY OF OPERATION
The AD5590 is an analog I/O module. The output port contains sixteen 12-bit voltage output DAC channels. The DAC channels are divided into two groups of eight DACs, each of which can be programmed independently. Each group of DACs contains its own internal 2.5 V reference. The references are powered down by default allowing the use of external references, if required. Either internal reference can be powered up and used as a reference for the ADC section. This is achieved by connecting the appropriate VREFINx/VREFOUTx pin to VREFA. Because the VREFINx/ VREFOUTx pins have different input and output impedances it is not possible to use one internal reference for both DAC groups without buffering. The input port comprises a single, 12-bit, 1 MSPS ADC with 16 multiplexed input channels. The ADC contains a sequencer that allows it to sample any combination of the sixteen channels. The AD5590 also contains eight rail-to-rail low noise amplifiers. These amplifiers can be used independently or as part of signal condition for the input or output ports.
Resistor String
The resistor string section is shown in Figure 53. It is simply a string of resistors, each of Value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
R
R
R
TO OUTPUT AMPLIFIER
DAC SECTION
Sixteen DACs make up the output port of the AD5590. Each DAC consists of a string of resistors followed by an output buffer amplifier. The sixteen DACs are divided into two groups of eight with each group having its own internal 2.5 V reference with an internal gain of 2. Figure 52 shows a block diagram of the DAC architecture.
DACV DD REF (+) DAC REGISTER RESISTOR STRING REF (-) GND
OUTPUT AMPLIFIER (GAIN = +2)
R
R
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Figure 53. Resistor String
DAC Internal Reference
The DAC section has two on-chip 2.5 V references with an internal gain of 2, giving a full-scale output of 5 V. The on-board reference is off at power-up, allowing the use of an external reference. The internal references are enabled via a write to the appropriate control register (see Table 11). The internal references associated with each group of DACs are available at the VREFIN1/VREFOUT1 and VREFIN2/VREFOUT2 pins. A buffer is required if the reference output is used to drive external loads. When using the internal reference, it is recommended that a 100 nF capacitor be placed between the reference output and DACGND for reference stability. Individual channel power-down is not supported while using the internal reference.
VOUTx
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Figure 52. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by
D VOUT = VREFIN x N 2
The ideal output voltage when using the internal reference is given by
D VOUT = 2 x V REFOUT x N 2
DAC Output Amplifier
The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to DACVDD. The amplifier is capable of driving a load of 2 k in parallel with 1000 pF to DACGND. The source and sink capabilities of the output amplifier can be seen in Figure 13. The slew rate is 1.5 V/s with a 1/4 to 3/4 scale settling time of 10 s.
where: D = decimal equivalent of the binary code that is loaded to the DAC register (0 to 4095). N = 12.
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AD5590
ADC SECTION
The ADC section is a fast, 16-channel, 12-bit, single-supply, analog-to-digital converter. The ADC is capable of throughput rates of up to 1 MSPS when provided with a 20 MHz clock. The ADC section provides the user with an on-chip trackand-hold, analog-to-digital converter. The ADC section has 16 single-ended input channels with a channel sequencer, allowing the user to select a sequence of channels through which the ADC can cycle with each consecutive ASYNC falling edge. The serial clock input accesses data from the ADC, controls the transfer of data written to the ADC, and provides the clock source for the successive approximation ADC converter. The analog input range for the ADC is 0 V to VREFA or 0 V to 2 x VREFA depending on the status of Bit 1 in the control register. The ADC provides flexible power management options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by programming the power management bits in the ADC control register.
VIN0 A SW1 VIN15 ADCGND B 4k CONTROL LOGIC SW2
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CAPACITIVE DAC
COMPARATOR
Figure 55. ADC Conversion Phase
Analog Input
Figure 56 shows an equivalent circuit of the analog input structure of the ADC. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceed the supply rails by more than 200 mV. This causes these diodes to become forward biased and start conducting current into the substrate. 10 mA is the maximum current these diodes can conduct without causing irreversible damage to the ADC. Capacitor C1 in Figure 56 is typically about 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a switch (track-and-hold switch) and also includes the on resistance of the input multiplexer.
ADCV DD D1 VINx C1 4pF D2 CONVERSION PHASE--SWITCH OPEN TRACK PHASE--SWITCH CLOSED
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ADC CONVERTER OPERATION
The ADC is a 12-bit successive approximation analog-to-digital converter based around a capacitive DAC. The ADC can convert analog input signals in the range 0 V to VREFA or 0 V to 2 x VREFA. Figure 54 and Figure 55 show simplified schematics of the ADC. The ADC comprises control logic, SAR, and a capacitive DAC, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. Figure 54 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected VIN channel.
CAPACITIVE DAC A SW1 VIN15 ADCGND B 4k CONTROL LOGIC SW2
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R1
C2 30pF
Figure 56. Equivalent Analog Input Circuit
VIN0
COMPARATOR
Figure 54. ADC Acquisition Phase
The total resistance is typically about 400 . Capacitor C2 is the ADC sampling capacitor and typically has a capacitance of 30 pF. For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC low-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, drive the analog input from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. When no amplifier is used to drive the analog input, limit the source impedance to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases, and performance degrades (see Figure 28).
When the ADC starts a conversion (see Figure 55), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 57 shows the ADC transfer function.
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AD5590
ADC Transfer Function
The output coding of the ADC is either straight binary or twos complement, depending on the status of the LSB (range bit) in the ADC control register. The designed code transitions occur midway between successive LSB values (that is, 1 LSB, 2 LSBs, and so on). The LSB size is equal to VREFA/4096. The ideal transfer characteristic for the ADC when straight binary coding is selected is shown in Figure 57.
111...111 111...110
has been initiated. The write bit must be set to 0 to ensure the ADC control register is not accidentally overwritten, or the sequence operation interrupted. If the ADC control register is written to at any time during the sequence, then it must be ensured that the SEQ and shadow bits are set to 1 and 0, respectively to avoid interrupting the automatic conversion sequence. This pattern continues until the ADC is written to and the SEQ and shadow bits are configured with any bit combination except 1, 0. On completion of the sequence, the ADC sequencer returns to the first selected channel in the shadow register and commence the sequence again if uninterrupted. Rather than selecting a particular sequence of channels, a number of consecutive channels beginning with Channel 0 can also be programmed via the control register alone, without needing to write to the shadow register. This is possible if the SEQ and shadow bits are set to 1, 1. The channel address bits, ADD3 through ADD0, then determine the final channel in the consecutive sequence. The next conversion is on Channel 0, then Channel 1, and so on until the channel selected via the ADD3 through ADD0 address bits is reached. The cycle begins again on the next serial transfer provided the write bit is set to low or, if high, that the SEQ and shadow bits are set to 1, 0; then, the ADC continues its preprogrammed automatic sequence uninterrupted. Regardless of which channel selection method is used, the 16-bit word output from the ADC during each conversion always contains the channel address that the conversion result corresponds to, followed by the 12-bit conversion result (see the Serial Interface section).
111...000 011...111 1LSB = VREF /4096
000...010 000...001 000...000 0V
1LSB
+VREF - 1LSB
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ANALOG INPUT VREF IS EITHER VREFA OR 2 x VREFA
Figure 57. Straight Binary Transfer Characteristic
011...111 011...110
ADC CODE
000...001 000...000 111...111 100...010 100...001 100...000 1LSB = 2 x VREFA/4096
Digital Inputs
The digital inputs applied to the ADC are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the ADCVDD + 0.3 V limit found on the analog inputs. Another advantage of ASCLK, ADIN, and ASYNC not being restricted by the ADCVDD + 0.3 V limit is the fact that power supply sequencing issues are avoided. If ASYNC, ADIN, or ASCLK is applied before ADCVDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to ADCVDD.
ANALOG INPUT
Figure 58. Twos Complement Transfer Characteristic with VREFA VREFA Input Range
Analog Input Selection
Any one of 16 analog input channels can be selected for conversion by programming the multiplexer with the ADD3 to ADD0 address bits in the ADC control register. The channel configurations are shown in Table 23. The ADC can also be configured to automatically cycle through a number of channels as selected. The sequencer feature is accessed via the SEQ and shadow bits in the ADC control register (see Table 21). The ADC can be programmed to continuously convert on a selection of channels in ascending order. The analog input channels to be converted on are selected through programming the relevant bits in the shadow register (see Table 26). The next serial transfer then acts on the sequence programmed by executing a conversion on the lowest channel in the selection. The next serial transfer results in a conversion on the next highest channel in the sequence, and so on. It is not necessary to write to the ADC control register once a sequencer operation
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-VREFA + 1LSB +VREFA - 1LSB VREFA - 1LSB
VDRIVE
The ADC has the VDRIVE feature, which controls the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the ADC is operated with a VDD of 5 V, the VDRIVE pin could be powered from a 3 V supply. The ADC has better dynamic performance with a VDD of 5 V while still being able to interface to 3 V processors. Care should be taken to ensure that VDRIVE does not exceed ADCVDD by more than 0.3 V (see the Absolute Maximum Ratings section).
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AD5590
Reference Section
An external reference source should be used to supply the 2.5 V reference to the ADC. Errors in the reference source results in gain errors in the ADC transfer function and adds to the specified full-scale errors of the ADC. A capacitor of at least 0.1 F should be placed on the VREFA pin. Suitable reference sources for the ADC include the AD780, REF193, and the AD1852. If 2.5 V is applied to the VREFA pin, the analog input range can either be 0 V to 2.5 V or 0 V to 5 V, depending on the range bit in the control register. The parts are fully specified to operate from a single 5.0 V supply, or 2.5 V dual supplies. The ability to swing rail-to-rail at both the input and output enables designers to buffer CMOS ADCs, DACs, ASICs, and other wide output swing devices in low power, single-supply systems. The amplifiers in the AD5590 are fully independent of the DAC and ADC sections. If some or all of the amplifiers are not required, connect them as a grounded unity-gain buffer, as shown in Figure 59.
AMPLIFIER SECTION
The operational amplifiers in the AD5590 are micropower, rail-to-rail input and output amplifiers that feature low supply current, low input voltage, and low current noise.
Figure 59. Configuration for Unused Amplifiers
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AD5590 SERIAL INTERFACE
The AD5590 contains independent serial interfaces for the ADC and DAC sections. The ADC uses the ASYNC, ASCLK, ADIN, and ADOUT pins. The VDRIVE pin allows the user to determine the output voltage of logic high signals. The DAC uses DSCLK, DDIN, DSYNC1, DSYNC2, LDAC, and CLR. The 16 analog input channels use the ADC interface. The 16 output channels use the DAC interface. The 16 output channels are divided into two groups of eight channels, which can be controlled independently. Each group has its own set of control registers. When addressing the DAC control registers, the serial data should be framed by DSYNC1 to access the control registers for DAC0 to DAC7 and framed by DSYNC2 to access the control registers for DAC8 to DAC15. The interfaces are compatible with SPI(R), QSPITM, MICROWIRETM, and most DSPs. of operation. At this stage, the DSYNCx line can be kept low or be brought high. In either case, it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of DSYNCx can initiate the next write sequence.
DAC Input Shift Register
The input shift register is 32 bits wide (see Figure 61). The first four bits are don't cares. The next four bits are the command bits, C3 to C0 (see Table 11), followed by the 4-bit DAC address, A3 to A0 (see Table 12), and finally the 12-bit data-word. The data-word comprises the 12-bit input code followed by eight don't care bits. These data bits are transferred to the DAC register on the 32nd falling edge of DSCLK.
Table 11. DAC Command Definitions
Command C3 C2 C1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 ... 1 0 1 1 1 1 0 0 ... 1 1 0 0 1 1 0 0 ... 1 C0 0 1 0 1 0 1 0 1 0 1 ... 1 Description Write to Input Register n Update DAC Register n Write to Input Register n, update all (Software LDAC) Write to and update DAC Channel n Power down/power up DAC Load clear code register Load LDAC register Reset (power-on reset) Set up internal REF register Reserved Reserved Reserved
ACCESSING THE DAC BLOCK
Figure 4 shows a timing diagram of a typical write sequence to the DAC block. The write sequence begins by bringing one or both of the DSYNC lines low. If DSYNC1 is brought low, the data is written to the DAC block containing DAC0 to DAC7. If DSYNC2 is brought low, the data is written to the DAC block containing DAC8 to DAC15. If both DSYNC1 and DSYNC2 are brought low, the data is written into both blocks simultaneously. Figure 60 shows how the serial interface is arranged.
CLR
LDAC
DSYNC1 DSCLK DDIN
GROUP 1 CONTROL REGISTERS
DAC 0
VOUT0
Table 12. DAC Address Commands
DAC 7 VOUT7
Address (n) A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 A0 0 1 0 1 0 1 0 1 1
Selected DAC Channel DSYNC1 Low DSYNC2 Low DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 DAC0 to DAC7 DAC8 DAC9 DAC10 DAC11 DAC12 DAC13 DAC14 DAC15 DAC8 to DAC15
DAC 15
VOUT15
Figure 60. DAC Serial Interface Configuration
Data from the DDIN line is clocked into the 32-bit shift register on the falling edge of DSCLK. The serial clock frequency can be as high as 50 MHz, making the AD5590 compatible with high speed DSPs. On the 32nd falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in DAC register contents and/or a change in the mode
DB31 (MSB) X X X X C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7
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DSYNC2
GROUP 2 CONTROL REGISTERS
DAC 8
VOUT8
DB0 (LSB) D6 D5 D4 D3 D2 D1 D0 X X X X X X X X
DATA BITS
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COMMAND BITS
ADDRESS BITS
Figure 61. DAC Input Register Contents
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AD5590
DSYNC Interrupt
In a normal write sequence, the DSYNCx line is kept low for 32 falling edges of DSCLK, and the DAC is updated on the 32nd falling edge and rising edge of DSYNCx. However, if DSYNCx is brought high before the 32nd falling edge, this acts as an interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 63). Table 11). These modes are software-programmable by setting Bit DB9 and Bit DB8 in the control register. Table 15 shows how the state of the bits corresponds to the mode of operation of the device. Any or all DACs (DAC0 to DAC7 in Block 1 or DAC8 to DAC15 in Block 2) can be powered down to the selected mode by setting the corresponding eight bits to 1. See Table 16 for the contents of the input shift register during powerdown/power-up operation. When using the internal reference, only all channel power-down to the selected modes is supported. When both bits are set to 0, each block works normally with its normal power consumption of 1.3 mA at 5 V. However, for the three power-down modes, the supply current of each block falls to 0.4 A at 5 V. Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the DAC is known while it is in power-down mode. There are three different options. The output is connected internally to GND through either a 1 k or a 100 k resistor, or it is left open-circuited (three-state). The output stage is illustrated in Figure 62.
RESISTOR STRING DAC
DAC Internal Reference Register
The on-board references in the DAC blocks are off at power-up by default. This allows the use of an external reference if the application requires it. The on-board references can be turned on or off by a user-programmable internal REF register by setting Bit DB0 high or low (see Table 13). Command 1000 is reserved for setting the internal REF register (see Table 11).
DAC Power-On Reset
The DAC blocks contain a power-on reset circuit that controls the output voltage during power-up. The DAC outputs power up to 0 V. The output remains powered up at this level until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. There is also a software executable reset function that resets the DAC to the power-on reset code. Command 0111 is reserved for this reset function (see Table 11). Any events on LDAC or CLR during power-on reset are ignored.
AMPLIFIER
VOUT
POWER-DOWN CIRCUITRY
DAC Power-Down Modes
The DAC block contains four separate modes of operation. Command 0100 is reserved for the power-down function (see
Figure 62. Output Stage During Power-Down
DSCLK
DSYNCx
DDIN
DB31
DB0
DB31
DB0
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INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 32ND FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 32ND FALLING EDGE
Figure 63. SYNC Interrupt Facility
Table 13. DAC Internal Reference Register
Internal REF Register (DB0) 0 1 Action Reference off (default) Reference on
Table 14. DAC 32-Bit Input Shift Register Contents for Reference Setup Command
MSB DB31 to DB28 X Don't care DB27 DB26 DB25 DB24 1 0 0 0 Command bits (C3 to C0) DB23 DB22 DB21 DB20 X X X X Address bits (A3 to A0)--don't care DB19 to DB1 X Don't care LSB DB0 1/0 Internal REF register
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RESISTOR NETWORK
AD5590
The bias generator of the selected DAC(s), output amplifier, resistor string, and other associated linear circuitry are shut down when the power-down mode is activated. The internal reference is powered down only when all channels are powered down. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 s for DACVDD = 5 V. Any combination of DACs can be powered up by setting PD1 and PD0 to 0 (normal operation). The output powers up to the value in the input register (LDAC low) or to the value in the DAC register before powering down (LDAC high). the user-configurable CLR register and sets the analog outputs accordingly. This function can be used in system calibration to load zero scale, midscale, or full scale to all channels together. These clear code values are user-programmable by setting Bit DB1 and Bit DB0 in the CLR control register (see Table 17). The default setting clears the outputs to 0 V. Command 0101 is reserved for loading the clear code register (see Table 11). The DAC exits clear code mode on the 32nd falling edge of the next write to the DAC. If CLR is activated during a write sequence, the write is aborted. The CLR pulse activation time--the falling edge of CLR to when the output starts to change--is typically 280 ns. However, if outside the DAC linear region, it typically takes 520 ns after executing CLR for the output to start changing. See Table 18 for contents of the input shift register during the loading clear code register operation.
DAC Clear Code Register
The DAC blocks have a hardware CLR pin that is an asynchronous clear input for all 16 DACs. The CLR input is falling edge sensitive. Bringing the CLR line low clears the contents of the input register and the DAC registers to the data contained in Table 15. DAC Power-Down Modes of Operation
DB9 0 0 1 1 DB8 0 1 0 1 Operating Mode Normal operation Power-down modes: 1 k to GND 100 k to GND Three-state
Table 16. DAC 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function
MSB DB31 to DB28 X Don't care LSB DB19 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 to DB10 DB9 0 1 0 0 X X X X X PD1 Command bits (C3 to C0) Address bits (A3 to A0)-- don't care Don't care DB8 PD0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DAC DAC DAC DAC DAC DAC DAC DAC H G F E D C B A Power-down/power-up channel selection--set bit to 1 to select
Power-down mode
Table 17. DAC Clear Code Register
DB1 CR1 0 0 1 1 Clear Code Register DB0 CR0 0 1 0 1
Clears to Code 0x0000 0x0800 0x0FFF No operation
Table 18. DAC 32-Bit Input Shift Register Contents for Clear Code Function
MSB DB31 to DB28 X Don't care DB27 DB26 DB25 DB24 0 1 0 1 Command bits (C3 to C0) DB23 DB22 DB21 DB20 X X X X Address bits (A3 to A0)--don't care DB19 to DB2 X Don't care LSB DB1 DB0 CR1 CR0 Clear code register
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AD5590
LDAC Function
The outputs of all DACs can be updated simultaneously using the hardware LDAC pin. Synchronous LDAC: After new data is read, the DAC registers are updated on the falling edge of the 32nd DSCLK pulse. LDAC can be permanently low or pulsed as in Figure 4. Asynchronous LDAC: The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register. Alternatively, the outputs of all DACs can be updated simultaneously using the software LDAC function by writing to Input Register n and updating all DAC registers. Command 0011 is reserved for this software LDAC function. An LDAC register gives the user extra flexibility and control over the hardware LDAC pin. This register allows the user to Table 19. LDAC Register
LDAC Bits (DB7 to DB0) 0 1 LDAC Pin 1/0 X--don't care LDAC Operation Determined by LDAC pin. DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0.
select which combination of channels to simultaneously update when the hardware LDAC pin is executed. Setting the LDAC bit register to 0 for a DAC channel means that this channel's update is controlled by the LDAC pin. If this bit is set to 1, this channel updates synchronously; that is, the DAC register is updated after new data is read, regardless of the state of the LDAC pin. It effectively registers the LDAC pin as being tied low. (See Table 19 for the LDAC register mode of operation.) This flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. Writing to the DAC using Command 0110 loads the 8-bit LDAC register (DB7 to DB0). The default for each channel is 0, that is, the LDAC pin works normally. Setting the bits to 1 means the DAC channel is updated regardless of the state of the LDAC pin. See Table 20 for the contents of the input shift register during the LDAC register mode of operation.
Table 20. DAC 32-Bit Input Shift Register Contents for LDAC Register Function
MSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 X 0 1 1 0 X X X X Command bits (C3 to C0) Don't Address bits (A3 to A0)-- care don't care LSB DB19 to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A Don't Setting LDAC bit to 1 overrides LDAC pin care
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AD5590
ACCESSING THE ADC BLOCK
The ADC register can be accessed via the serial interface using the ASCLK , ADIN, ADOUT, and ASYNC pins. The VDRIVE pin can be used to dictate the logic levels of the output pins, allowing the ADC to be interfaced to a 3 V DSP while the ADC is operating at 5 V. The conversion is initiated on the falling edge of ASYNC and the track-and-hold enters hold mode as described in the Serial Interface section. The data presented to the ADC on the ADIN line during the first 12 clock cycles of the data transfer is loaded to the ADC control register (provided the write bit is 1). If the previous write had SEQ = 0 and shadow = 1, the data presented on the ADIN line on the next 16 ASCLK cycles is loaded into the shadow register. The ADC remains fully powered up in normal mode at the end of the conversion as long as PM1 and PM0 are set to 1 in the write transfer during that conversion. To ensure continued operation in normal mode, PM1 and PM0 are both loaded with 1 on every data transfer. Sixteen serial clock cycles are required to complete the conversion and access the conversion result. The track-and-hold returns to track on the 14th ASCLK falling edge. ASYNC can then idle high until the next conversion or can idle low until sometime prior to the next conversion, (effectively idling ASYNC low). When a data transfer is complete (ADOUT has returned to three-state, weak/TRI bit = 0), another conversion can be initiated by bringing ASYNC low again after the quiet time, tQUIET, has elapsed.
ADC Modes of Operation
The ADC has a number of different modes of operation. These modes are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/ throughput rate ratio for differing application requirements. The mode of operation of the ADC is controlled by the power management bits, PM1 and PM0, in the ADC control register, as detailed in Table 21. When power supplies are first applied to the ADC, ensure that the ADC is placed in the required mode of operation (see the Powering Up the ADC section).
Normal Mode (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate performance because the user does not have to worry about any power-up times with the ADC remaining fully powered at all times. Figure 64 shows the general diagram of the operation of the ADC in this mode.
ASYNC 1 ASCLK ADOUT
CHANNE L IDENTIFIER BITS + CONVERSION RESULT
Full Shutdown (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the ADC is powered down. The ADC retains information in the ADC control register during full shutdown. The ADC remains in full shutdown until the power management bits in the control register, PM1 and PM0, are changed. If a write to the ADC control register occurs while the ADC is in full shutdown, with the power management bits changed to PM0 = PM1 = 1, normal mode, the ADC begins to power up on the ASYNC rising edge. The track-and-hold that was in hold while the ADC was in full shutdown return to track on the 14th ASCLK falling edge. To ensure that the ADC is fully powered up, tPOWER-UP (t12) should elapse before the next ASYNC falling edge. Figure 65 shows the general diagram for this sequence.
12
16
ADIN
DATA IN TO CONTROL/SHADOW REGISTER
07691-064
NOTES 1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES. 2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES.
Figure 64. ADC Normal Mode Operation
PART IS IN FULL PART BEGINS TO POWER UP ON ASYNC PART IS FULLY POWERED UP SHUTDOWN RISING EDGE AS PM1 = 1, PM0 = 1 ONCE TPOWER UP HAS ELAPSED
t12
ASYNC 1 ASCLK ADOUT
CHANNE L IDENTIFIER BITS + CONVERSION RESULT
14
16
1
14
16
ADIN
DATA IN TO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS, PM1 = 1, PM0 = 1
DATA IN TO CONTROL/SHADOW REGISTER TO KEEP PART IN NORMAL MODE, LOAD PM1 = 1, PM0 = 1 IN CONTROL REGISTER
07691-065
Figure 65. Full Shutdown Mode Operation
Rev. 0 | Page 34 of 44
AD5590
AutoShutdown (PM1 = 0, PM0 = 1)
In this mode, the ADC automatically enters shutdown at the end of each conversion when the ADC control register is updated. When the ADC is in shutdown, the track-and-hold is in hold mode. Figure 66 shows the general diagram of the operation of the ADC in this mode. In shutdown mode, all internal circuitry on the ADC is powered down. The ADC retains information in the ADC control register during shutdown. The ADC remains in shutdown until the next ASYNC falling edge it receives. On this ASYNC falling edge, the track-and-hold that was in hold while the ADC was in shutdown returns to track. Wake-up time from autoshutdown is 1 s, and the user should ensure that 1 s has elapsed before attempting a valid conversion. When running the ADC with a 20 MHz clock, one dummy cycle of 16 x ASCLKs should be sufficient to ensure that the ADC is fully powered up. During this dummy cycle, the contents of the ADC control register should remain unchanged; therefore, the write bit should be 0 on the ADIN line. This dummy cycle effectively halves the throughput rate of the ADC, with every other conversion result being valid. In this mode, the power consumption of the ADC is greatly reduced with the ADC entering shutdown at the end of each conversion. When the ADC control register is programmed to move into autoshutdown, it does so at the end of the conversion. The user can move the ADC in and out of the low power state by controlling the ASYNC signal.
PART ENTERS SHUTDOWN ON ASYNC RISING EDGE AS PM1 = 0, PM0 = 1 PART BEGINS TO POWER UP ON ASYNC FALLING EDGE
Autostandby (PM1 = PM0 = 0)
In this mode, the ADC automatically enters standby mode at the end of each conversion when the ADC control register is updated. Figure 67 shows the general diagram of the operation of the ADC in this mode. When the ADC is in standby, portions of the ADC are powered down, but the on-chip bias generator remains powered up. The ADC retains information in the ADC control register during standby. The ADC remains in standby until it receives the next ASYNC falling edge. On this ASYNC falling edge, the track and hold that was in hold while the ADC was in standby returns to track. Wake-up time from standby is 1 s; the user should ensure that 1 s has elapsed before attempting a valid conversion on the ADC in this mode. When running the ADC with a 20 MHz clock, one dummy cycle of 16 x ASCLKs should be sufficient to ensure the ADC is fully powered up. During this dummy cycle, the contents of the ADC control register should remain unchanged; therefore, the write bit should be set to 0 on the ADIN line. This dummy cycle effectively halves the throughput rate of the ADC with every other conversion result being valid. In this mode, the power consumption of the ADC is greatly reduced with the ADC entering standby at the end of each conversion. When the ADC control register is programmed to move into autostandby, it does so at the end of the conversion. The user can move the ADC in and out of the low power state by controlling the ASYNC signal.
PART ENTERS SHUTDOWN ON CS RISING EDGE AS PM1 = 0, PM0 = 1
PART IS FULLY POWERED UP
ASYNC 1 ASCLK 16 1
DUMMY CONVERSION 16 1 16
ADOUT
CHANNE IDENTIFIER BITS + CONVERSION RESU L LT
INVALID DATA
CHANNE IDENTIFIER BITS + CONVERSION RESU L LT
CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS, PM1 = 0, PM0 = 1
CONTROL REGISTER CONTENTS SHOULD NOT CHANGE, WRITE BIT = 0
TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1 IN CONTROL REGISTER OR SET WRITE BIT = 0
Figure 66. Autoshutdown Mode Operation
PART ENTERS STANDBY ON ASYNC RISING EDGE AS PM1 = 0, PM0 = 0
PART BEGINS TO POWER UP ON ASYNC FALLING EDGE
PART IS FULLY POWERED UP
PART ENTERS STANDBY ON ASYNC RISING EDGE AS PM1 = 0, PM0 = 0
ASYNC 1 ASCLK ADOUT 12 16 1
DUMMY CONVERSION 12 16 1 12 16
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
INVALID DATA
CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS, PM1 = 0, PM0 = 0
CONTROL REGISTER CONTENTS SHOULD REMAIN UNCHANGED, WRITE BIT = 0
TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 0 IN CONTROL REGISTER
Figure 67. Autostandby Mode Operation
Rev. 0 | Page 35 of 44
07691-067
ADIN
DATA IN TO CONTROL/SHADOW REGISTER
DATA IN TO CONTROL/SHADOW REGISTER
07691-066
ADIN
DATA IN TO CONTROL/SHADOW REGISTER
DATA IN TO CONTROL/SHADOW REGISTER
AD5590
Powering Up the ADC
When supplies are first applied to the ADC, the ADC can power up in any of the operating modes of the ADC. To ensure that the ADC is placed into the required operating mode, the user should perform a dummy cycle operation, as outlined in Figure 68. The three dummy conversion operations outlined in Figure 68 must be performed to place the ADC into either of the automatic modes. The first two conversions of this dummy cycle operation are performed with the ADIN line tied high, and for the third conversion of the dummy cycle operation, the user writes the desired control register configuration to the ADC to place the ADC into the required automode. On the third ASYNC rising edge after the supplies are applied, the control register contains the correct information and valid data results from the next conversion. Therefore, to ensure the ADC is placed into the correct operating mode when supplies are first applied to the ADC, the user must first issue two serial write operations with the ADIN line tied high. On the third conversion cycle, the user can then write to the ADC control register to place the ADC into any of the operating modes. To guarantee that the ADC control register contains the correct data, do not write to the shadow register until the fourth conversion cycle after the supplies are applied to the ADC. If the user wants to place the ADC into either normal mode or full shutdown mode, the second dummy cycle with ADIN tied high can be omitted from the three dummy conversion operation outlined in Figure 68.
Interfacing to the ADC
Figure 2 shows the detailed timing diagram for serial interfacing to the ADC. The serial clock provides the conversion clock and also controls the transfer of information to and from the ADC during each conversion. The ASYNC signal initiates the data transfer and conversion process. The falling edge of ASYNC puts the track and hold into hold mode, takes the bus out of three-state, and the analog input is sampled at this point. The conversion is also initiated at this point and requires 16 ASCLK cycles to complete. The track and hold returns to track on the 14th ASCLK falling edge as shown in Figure 2 at Point B, except when the write is to the shadow register, in which case the track and hold does not return to track until the rising edge of ASYNC, that is, Point C in Figure 72. On the 16th ASCLK falling edge, the ADOUT line goes back into three-state (assuming the weak/TRI bit is set to 0). Sixteen serial clock cycles are required to perform the conversion process and to access data from the ADC. The 12 bits of data are preceded by the four channel address bits (ADD3 to ADD0), identifying which channel the conversion result corresponds to. ASYNC going low provides Address Bit ADD3 to be read in by the microprocessor or DSP. The remaining address bits and data bits are then clocked out by subsequent ASCLK falling edges beginning with the second Address Bit ADD2; thus, the first ASCLK falling edge on the serial clock has Address Bit ADD3 provided and also clocks out Address Bit ADD2. The final bit in the data transfer is valid on the 16th falling edge, having being clocked out on the previous (15th) falling edge.
CORRECT VALUE IN CONTROL REGISTER VALID DATA FROM NEXT CONVERSION USER CAN WRITE TO SHADOW REGISTER IN NEXT CONVERSION
ASYNC
DUMMY CONVERSION 1 12 16 1
DUMMY CONVERSION 12 16 1 12 16
ASCLK ADOUT
INVALID DATA
INVALID DATA
INVALID DATA
ADIN
KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS
CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCK EDGES
Figure 68. Placing the ADC into the Required Operating Mode after Supplies are Applied
Rev. 0 | Page 36 of 44
07691-068
DATA IN TO CONTROL
AD5590
ADC Control Register
The control register on the ADC is a 12-bit, write-only register. Data is loaded from the ADIN pin of the ADC on the falling edge of ASCLK. The data is transferred on the ADIN line at the same time as the conversion result is read from the ADC. The data transferred on the ADIN line corresponds to the ADC configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after ASYNC falling edge) is loaded to the ADC control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 21. Writing of information to the ADC control register takes place on the first 12 falling edges of ASCLK in a data transfer, assuming the MSB, that is, the write bit, has been set to 1. If the ADC control register is programmed to use the shadow register, writing of information to the shadow register takes place on all 16 ASCLK falling edges in the next serial transfer (see Figure 72). The shadow register is updated on the rising edge of ASYNC and the track-and-hold begins to track the first channel selected in the sequence. If the weak/TRI bit in the ADC control register is set to 1, rather than returning to true three-state upon the 16th ASCLK falling edge, the ADOUT line is instead pulled weakly to the logic level corresponding to ADD3 of the next serial transfer. This is done to ensure that the MSB of the next serial transfer is set up in
Table 21. ADC Control Register
MSB DB11 Write DB10 SEQ DB9 ADD3 DB8 ADD2 DB7 ADD1 DB6 ADD0 DB5 PM1 DB4 PM0 DB3 Shadow DB2 Weak/TRI DB1 Range LSB DB0 Coding
time for the first ASCLK falling edge after the ASYNC falling edge. If the weak/TRI bit is set to 0 and the ADOUT line has been in true three-state between conversions, then depending on the particular DSP or microcontroller interfacing to the ADC, the ADD3 address bit may not be set up in time for the DSP/microcontroller to clock it in successfully. In this case, ADD3 is only driven from the falling edge of ASYNC and must then be clocked in by the DSP on the following falling edge of ASCLK. However, if the weak/TRI bit had been set to 1, then although ADOUT is driven with the ADD3 address bit from the last conversion, it is nevertheless so weakly driven that another device may still take control of the bus. It does not lead to a bus contention (for example, a 10 k pull-up or pull-down resistor would be sufficient to overdrive the logic level of ADD3 between conversions), and all 16 channels may be identified. However, if this does happen and another device takes control of the bus, it is not guaranteed that ADOUT becomes fully driven to ADD3 again in time for the read operation when control of the bus is taken back. This is especially useful if using an automatic sequence mode to identify to which channel each result corresponds. Obviously, if only the first eight channels are in use, the ADD3 address bit does not need to be decoded, and whether it is successfully clocked in as a 1 or 0 does not matter as long as it is still counted by the DSP/microcontroller as the MSB of the 16-bit serial transfer.
Table 22. ADC Control Register Bit Functions
Bit 11 Name Write Description The value written to this bit of the control register determines whether the following 11 bits are loaded to the control register or not. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, the remaining 11 bits are not loaded to the control register, therefore it remains unchanged. The SEQ bit in the control register is used in conjunction with the shadow bit to control the use of the sequencer function and to access the shadow register (see Table 25). These four address bits are loaded at the end of the current conversion sequence and select which analog input channel is to be converted on in the next serial transfer, or can select the final channel in a consecutive sequence, as described in Table 25. The selected input channel is decoded as shown in Table 23. The address bits corresponding to the conversion result are also output on ADOUT prior to the 12 bits of data (see the Serial Interface section). The next channel to be converted on is selected by the mux on the 14th ASCLK falling edge. These two power management bits decode the mode of operation of the ADC, as shown in Table 24. The shadow bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer function and access the shadow register (see Table 25). This bit selects the state of the ADOUT line at the end of the current serial transfer. If it is set to 1, the ADOUT line is weakly driven to the ADD3 channel address bit of the ensuing conversion. If this bit is set to 0, ADOUT returns to threestate at the end of the serial transfer. See the Serial Interface section for more details. This bit selects the analog input range to be used on the ADC. If it is set to 0, then the analog input range extends from 0 V to 2 x VREFA. If it is set to 1, then the analog input range extends from 0 V to VREFA (for the next conversion). For 0 V to 2 x VREFA, ADCVDD = 4.75 V to 5.25 V. This bit selects the type of output coding the ADC uses for the conversion result. If this bit is set to 0, the output coding for the ADC is twos complement. If this bit is set to 1, the output coding from the ADC is straight binary (for the next conversion).
Rev. 0 | Page 37 of 44
10 9:6
SEQ ADD3:ADD0
5, 4 3 2
PM1, PM0 Shadow Weak/TRI
1
Range
0
Coding
AD5590
Table 23. ADC Channel Selection
ADD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ADD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ADD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ADD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Channel VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 VIN12 VIN13 VIN14 VIN15
Table 24. ADC Power Mode Selection
PM1 1 1 PM0 1 0 Mode Normal operation. In this mode, the ADC remains in full power mode regardless of the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the ADC. Full shutdown. In this mode, the ADC is in full shut down mode, with all circuitry on the ADC powered down. The ADC retains the information in the control register while in full shutdown. The ADC remains in full shutdown until these bits are changed in the control register. Autoshutdown. In this mode, the ADC automatically enters shutdown mode at the end of each conversion when the control register is updated. Wake-up time from shutdown is 1 s and the user should ensure that 1 s has elapsed before attempting to perform a valid conversion on the ADC in this mode. Autostandby. In this standby mode, portions of the ADC are powered down, but the on-chip bias generator remains powered up. This mode is similar to autoshutdown and allows the ADC to power up within one dummy cycle, that is, 1 s with a 20 MHz ASCLK.
0
1
0
0
ADC Sequencer Operation
The configuration of the SEQ and shadow bits in the control register allows the user to select a particular mode of operation of the sequencer function. Table 25 outlines the four modes of operation of the sequencer.
Table 25. ADC Sequence Selection
SEQ 0 Shadow 0 Sequence Type This configuration means the sequence function is not used. The analog input channel selected for each individual conversion is determined by the contents of the channel address bits, ADD0 to ADD3, in each prior write operation. This mode of operation reflects the normal operation of a multichannel ADC, without sequencer function being used, where each write to the ADC selects the next channel for conversion (see Figure 69). This configuration selects the shadow register for programming. After the write to the control register, the following write operation loads the contents of the shadow register. This programs the sequence of channels to be converted on continuously with each successive valid ASYNC falling edge (see the shadow register, Table 26, and Figure 70). The channels selected need not be consecutive. If the SEQ and shadow bits are set in this way, the sequence function is not interrupted upon completion of the write operation. This allows other bits in the control register to be altered while in a sequence without terminating the cycle. This configuration is used in conjunction with the channel address bits, ADD3 to ADD0, to program continuous conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel, as determined by the channel address bits in the control register (see Figure 71).
0
1
1 1
0 1
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AD5590
ADC Shadow Register
The shadow register on the ADC is a 16-bit, write-only register. Data is loaded from the ADIN pin of the ADC on the falling edge of ASCLK. The data is transferred on the ADIN line at the same time as a conversion result is read from the ADC. This requires 16 serial falling edges for the data transfer. The information is clocked into the shadow register, provided that the SEQ and shadow bits were set to 0 and 1, respectively, in the previous write to the control register. MSB denotes the first bit in the data stream. Each bit represents an analog input from Channel 0 through to Channel 15. A sequence of channels can be selected through which the ADC cycles with each consecutive ASYNC falling edge after the write to the shadow register. To select a sequence of channels, the associated channel bit must be set for each analog input. The ADC continuously cycles through the selected channels in ascending order, beginning with the lowest channel, until a write operation occurs (that is, the write bit is set to 1) with the SEQ and shadow bits configured in any way except 1, 0 (see Table 25). The bit functions are outlined in Table 26. Figure 69 reflects the normal operation of a multichannel ADC, where each serial transfer selects the next channel for conversion. In this mode of operation, the sequencer function is not used. Figure 70 shows how to program the ADC to continuously convert on a particular sequence of channels. To exit this mode of operation and revert back to the normal mode of operation of a multichannel ADC (as outlined in Figure 69), ensure the write bit = 1 and the SEQ = shadow = 0 on the next serial transfer. Figure 71 shows how a sequence of consecutive channels can be converted without having to program the shadow register or write to the ADC on each serial transfer. Again, to exit this mode of operation and revert back to the normal mode of operation of a multichannel ADC (as outlined in Figure 69), ensure the write bit = 1 and the SEQ = shadow = 0 on the next serial transfer.
POWER ON DUMMY CONVERSIONS ADIN = ALL 1s
POWER ON
DUMMY CONVERSIONS ADIN = ALL 1s
ASYNC
ADIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE SELECT CHANNEL ADD3 TO CHANNEL ADD0 FOR CONVERSION, SEQ = 0 SHADOW = 1
ASYNC
ADOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED CHANNEL ADD3 TO CHANNEL ADD0 ADIN: WRITE TO SHADOW REGISTER, SELECTING WHICH CHANNELS TO CONVERT ON; CHANNELS SELECTED NEED NOT BE CONSECUTIVE WRITE BIT = 0 CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS WRITE BIT = 1, SEQ = 1, SHADOW = 0 CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS BUT ALLOWS RANGE, CODING, AND SO ON, TO CHANGE IN THE CONTROL REGISTER WITHOUT INTERRUPTING THE SEQUENCE PROVIDED, SEQ = 1 SHADOW = 0
ASYNC
WRITE BIT = 0
WRITE BIT = 0
Figure 70. Continuous Conversions
POWER ON
DUMMY CONVERSIONS ADIN = ALL 1s
ASYNC
ADIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE SELECT CHANNEL ADD3 TO CHANNEL ADD0 FOR CONVERSION, SEQ = 1 SHADOW = 1
ADOUT: CONVERSION RESULT FROM CHANNEL 0 ASYNC CONTINUOUSLY CONVERTS ON A CONSECUTIVE SEQUENCE OF CHANNELS FROM CHANNEL 0 UP TO AND INCLUDING THE PREVIOUSLY SELECTED CHANNEL ADD3 TO CHANNEL ADD0 IN THE CONTROL REGISTER WRITE BIT = 1, SEQ = 1, SHADOW = 0 ASYNC CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS BUT ALLOWS RANGE, CODING, AND SO ON, TO CHANGE IN THE CONTROL REGISTER WITHOUT INTERRUPTING THE SEQUENCE PROVIDED, SEQ = 1, SHADOW = 0 WRITE BIT = 0
ASYNC
ADIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE SELECT CHANNEL ADD3 TO CHANNEL ADD0 FOR CONVERSION, SEQ = SHADOW = 0
ADOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED CHANNEL ADD3 TO CHANNEL ADD0 ASYNC ADIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE SELECT CHANNEL ADD3 TO CHANNEL ADD0 FOR CONVERSION, SEQ = SHADOW = 0
WRITE BIT = 1, SEQ = SHADOW = 0
Figure 71. Continuous Conversion Without Programming the Shadow Register
Figure 69. Sequence Function Not Used
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07691-069
07691-071
WRITE BIT = 1, SEQ = 1, SHADOW = 0
07691-070
WRITE BIT = 1, SEQ = 1, SHADOW = 0
AD5590
Table 26. ADC Shadow Register Bits
MSB DB15 VIN0 DB14 VIN1 DB13 VIN2 DB12 VIN3 DB11 VIN4 DB10 VIN5 DB9 VIN6 DB8 VIN7 DB7 VIN8 DB6 VIN9 DB5 VIN10 DB4 VIN11 DB3 VIN12 DB2 VIN13 DB1 VIN14
C
LSB DB0 VIN15
ASYNC
t2
ASCLK 1 2 3 4
t6 t4
ADD2 ADD1 ADD0 DB11
tCONVERT
5 6 13 14 15 16
t3
ADOUT THREESTATE ADD3 VIN0
t7
DB10 DB2
t5
DB1
t11
DB0
ADIN
VIN1
VIN2
VIN3
VIN4
VIN5
VIN13
VIN14
VIN15
Figure 72. Writing to Shadow Register Timing Diagram
Rev. 0 | Page 40 of 44
07691-072
t9
FOUR IDENTIFICATION BITS
t10
t8
THREESTATE
AD5590
ADC Power vs. Throughput Rate
By operating the ADC in autoshutdown or autostandby mode, the average power consumption of the ADC decreases at lower throughput rates. Figure 73 shows how, as the throughput rate is reduced, the ADC remains in its shutdown state longer and the average power consumption over time drops accordingly. For example, if the ADC is operated in a continuous sampling mode with a throughput rate of 100 kSPS and an ASCLK of 20 MHz, with PM1 = 0 and PM0 = 1 (that is, the device is in autoshutdown mode), the power consumption is calculated as follows: the maximum power dissipation during normal operation is 12.5 mW. If the power-up time from autoshutdown is one dummy cycle, that is, 1 s, and the remaining conversion time is another cycle, that is, 1 s, the ADC dissipates 12.5 mW for 2 s during each conversion cycle. For the remainder of the conversion cycle, 8 s, the ADC remains in shutdown mode. The ADC dissipates 2.5 W for the remaining 8 s of the conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 s and the average power dissipated during each cycle is
2 8 x 12.5 mW + x 2.5 W = 2.502 mW 10 10 When operating the ADC in autostandby mode, PM1 = PM0 = 0 at 5 V, 100 kSPS, the ADC power dissipation is calculated as follows: the maximum power dissipation is 12.5 mW at 5 V during normal operation. The power-up time from autostandby is one dummy cycle, 1 s, and the remaining conversion time is another dummy cycle, 1 s. The ADC dissipates 12.5 mW for 2 s during each conversion cycle. For the remainder of the conversion cycle, 8 s, the ADC remains in standby mode dissipating 460 W for 8 s. If the throughput rate is 100 kSPS, the cycle time is 10 s and the average power dissipated during each conversion cycle is 2 8 x 12.5 mW + x W = 2.868 mW 10 10 Figure 73 shows the power vs. throughput rate when using the autoshutdown mode and autostandby mode with 5 V supplies. At the lower throughput rates, power consumption for the autoshutdown mode is lower than that for the autostandby mode, with the ADC dissipating less power when in shutdown compared to standby. However, as the throughput rate is increased, the ADC spends less time in power-down states; thus, the difference in power dissipated is negligible between modes.
10 ADCV DD = 5V AUTOSTANDBY AUTOSHUTDOWN 1
POWER (mV)
0.1
0
50
100
150
200
250
300
350
THROUGHPUT (kSPS)
Figure 73. Power vs. Throughput Rate in Autoshutdown and Autostandby Mode
Rev. 0 | Page 41 of 44
07691-073
0.01
AD5590 OUTLINE DIMENSIONS
10.00 BSC SQ A1 CORNER INDEX AREA
12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M
2.50 SQ
BALL A1 PAD CORNER TOP VIEW
8.80 BSC SQ
BOTTOM VIEW
0.60 REF 1.50 1.36 1.21 DETAIL A
0.80 BSC
0.65 REF 0.36 REF
DETAIL A
1.11 1.01 0.91
0.35 NOM 0.30 MIN
*0.50 0.45 0.40 BALL DIAMETER
0.12 MAX COPLANARITY SEATING PLANE
*COMPLIANT TO JEDEC STANDARDS MO-205-AC WITH THE EXCEPTION TO BALL DIAMETER.
Figure 74. 80-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-80-2) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5590BBC AD5590BBCZ 1 EVAL-AD5590EBZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 80-Ball CSP_BGA 80-Ball CSP_BGA Evaluation Board
Package Option BC-80-2 BC-80-2
Z = RoHS Compliant Part.
Rev. 0 | Page 42 of 44
011007-A
AD5590 NOTES
Rev. 0 | Page 43 of 44
AD5590 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07691-0-10/08(0)
Rev. 0 | Page 44 of 44

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